Tolerance Management and Characterization
 Accurate clock-tolerance is required by your "timing verifier". A precise and correct analysis of this timing information is essential for aggressively timed systems, since it forms the basis of numerous critical design decisions. ASA's specialized skill and experience in generating this information can reduce your development time and add substantially to the reliability of your design.
- Development of an accurate clock-tolerance budget for timing verification. Pessimistic estimates degrade performance. optimistic estimates yield an unstable design. Mike Williams ' 13 years of work in TE-analysis has resulted in a number of effective, proprietary methods for accurate tolerance-budgeting.
- Effective, high-precision measurement methods for low-amplitude jitter, jitter spectra, PLL characterization, etc.
- Evaluation and recommendation of measurement methods and instrumentation
- Parametric characterization
of device and interconnect timing. Simulator models are usually
inaccurate. Device data-sheets provide no usable information beyond
static delay tolerancing. All other timing data such as interconnect tolerancing and jitter/phase-noise distributions must be estimated or measured. We have solid experience defining solutions which provide this data. This experience ranges from simple fixtured sophisticated technology-assessment procedures, boards and systems.
- Analytical verifications/determination of your system timing margins.
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