Clock and Timing

Working closely with your design team, there are a number of effective contributions ASA can make early in your design-cycle. These include:

• Specification of high-precision clock distribution schemes and networks. From 5 to 1500 loads, from CMOS to ECL, we can design an effective solution for your design.

• Managing skew, jitter and other degradations of clock-precision/fidelity to very tight limits is our core technical skillset. We have a significant depth of experience with PLL-based designs.

• Clock-reception schemes, including methods that reduce the sensitivity of the state-architecture to clock tolerancing, or which exploit locality, correlation or tracking effects present in the clock-distribution network.

• Specification of timing-environment design ground rules for use by your design team during detailed logic design.

• Design reviews and sanity checks. A one- to three-day review of your methodology and design decisions can save expensive reiterations of the design. This has been particularly useful to our customers using PLLs.

Your specific need may not be on the short list above. If it involves timing, we can help you find a cost-effective solution to your problem. Click here to contact ASA.